|To address the challenges presented by next-generation systems and ASIC/SoC design, MCSC Foundation technology delivers performance/power/area comparable to Standard Cell Technology while providing unlimited flexibility for design.|
MCSC Foundation Technology are offered across different process nodes and FABs. Each building blocks (IPs) of Foundation Technology has consistent same metal configurability for design flexibility, functional changes with huge advantages over fixed functionality of Standard Cell IPs.
Metal Configurable Standard Cells
BaySand’s Metal Configurable Standard Cells (mcCORE) consists of a library of over 500 ASIC compatible standard cell logic functions. Implemented on a sea of gates, the library provides a comprehensive family of the fundamental metal configurable logic functions required to develop the digital logic and on-chip memory required of advanced ASIC, ASSP and SoC devices.
Functionally compatible with standard cell libraries, BaySand’s technology is not FPGA or Structured Logic but standard cell with patented technologies for high density metal configurable circuit routing, multi-Vt device support and multiple drive capability, delivering performance, power, cost, area density and time-to-market advantages over standard cell ASIC.
BaySand’s metal configurable cell library (mcCORE) is built around fine grained transistor level metal configuration (the Base Cell – BC) for all core logic cells. Based on the same transistor size as standard cell with minimum transistors per used logic function, it delivers better or equal performance, power and aerial density compared to standard cell ASIC while delivering on unparalleled flexibility for ECO’s, design and specification modifications, changing market requirements and families of products with only metal layer changes.
BaySand’s MCSC cell libraries are also fully compatible with Industry Standard EDA tools and methodologies such as synthesis, place and route, extraction, clock tree generation, etc. for seamless migration or integration of existing and new designs to BaySand’s technology.
BaySand’s Metal Configurable Standard Cells have been designed with maximum routing capability and flexibility providing highest density routing for rapid closure on place and route, timing closure and minimized number of metal layers required.
Patented MCSC Technology enables metal level selection of circuit drive strength without requiring base layer mask changes. This allows efficient matching of circuit performance to desired device performance with metal only design changes.
Only used logic is powered with no power to unused cells eliminating static power and minimizing overall design power consumption.
|Features||Standard Cell||BaySand mcCORE|
|Many Logic Functions|
|Multiple Drive Strength (1x, 2x, 4x etc)|
|Multiple Vt (LVt, RVt)|
|Low Power Design Support|
|Testability Scan FFs Support|
|Power Optimization Support|
|Design Flow & EDA Tool Support|
|RTL Synthesis for Power / Timing Optimization|
|Support for P&R Tools (Synopsys/Cadence)|
|STA / FV / IR / EM|
|Mask Required for Design||All Layers||4 Metal Layers|
The mcCORE are composed on Base Cell(BC) which has fixed transistors and up-to M1 layers. The cell functional changes and chip level signal routing between cells are accomplished by changing 4 customizable metal layers.
MCSC Memory Technology
BaySand’s MCSC memory support spans support for both off chip and on chip memory. On chip memory support includes Standard Cell compiled memories from memory compilers, BaySand’s Block Memory capability and metal configurable cell based Register Files serving a comprehensive range of memory requirements with the flexibility of our MCSC technology.
BaySand on Chip Memory Capability
Learn More About MCSC Memory Technology
For multiple products based on a metal configurable platform (mcPLATFORM), unused memory blocks are fully powered off, are fully available for routing and about 30% of areas are available for use for user logic design.
Using BaySand’s Xpresso IP Wizard, you can design MCSC configurable on-chip memory blocks to meet chip design requirements.
MCSC I/O Technology
BaySand’s metal configurable I/O technology provides I/O configurability for maximum chip I/O design flexibility and performance.
With features including fully configurable I/O banks with support for all I/O voltage standards, the ability for any I/O to be configured for input, output, power or ground, wire-bond or flip-chip capability, slot-less PWR/GND for pad limited designs, programmable drive strength, DDR/LVDS PHY capability anywhere on the I/O ring and more, your design can be adapted to multiple customer and market requirements with metal only reconfiguration.
I/O Standards Supported
I/O Voltage Supported
|Input (V)||Output (V)|
Configurable IO Features
|mcPLL is wide range PLL that can provide up to 9 output clocks, each of which can be configured to have different frequency and phase. It also support post-silicon configurability for frequency and phase to provide flexibility in system level debug or timing adjustment.|
mcPLL has following features:
- Programmable frequency and phase
- Programmable bandwidth
- Supports spread-spectrum reference clock tracking
- Supports spread-spectrum clock (SSC) generation
- Up to 9 independent outputs with various application from single reference clock
- Programmable duty cycle correction
- Support fractional division
- Support PLL cascading (e.g. Output of 1st PLL can be used for input reference clock for 2nd PLL)
- Can be placed in IO ring for easy floorplanning
MCSC Transceiver Technology
BaySand’s MCSC Transceiver Technology includes a metal configurable Physical Media Attach (PMA) sublayer with Communications Management Unit (CMU) and Physical Coding Sublayer (PCS).
BaySand Multi-Protocol SERDES Solution
| (Physical Medium Attachment)|
Analog RX, TX and CDR function block
|(Physical Coding Sublayer)|
Digital Protocol Sublayer
Digital Data Link Control
MCSC PMA Features
- Modular RX/TX channel + CMU (LC)
- Full-duplex transceivers
- Maximum serial data rates and input reference clocks are dependent on specific selected process node performance
- For serial data rate below 600 Mbps, oversampling is used
- Each RX/TX Channel has 3 mode:
- as data lane
- as TX clock generator (using the RX PLL)
- ref clock input
- TX PLL can be either
- Dynamic reconfiguration of PMA blocks
- Flexible reference clocking
BaySand provides a soft multi-protocol PCS to enable protocol optimization to your design. The design is optimized for power, performance and efficient aerial density for required protocols per design.
The digital PCS design is independent of the PMA. The modular multi-protocol PMA plus soft PCS allows efficient transceiver metal only reconfiguration and reuse.
Combining BaySand’s family of metal configurable digital interface IP’s, with BaySand’s MCSC transceiver technology provides the ultimate in flexibility in multi-product design.
Specific transceiver availability and performance characteristics are process node dependent. For details regarding a specific process node, please refer to MCSC Foundation Technology in the Solutions tab.
MCSC Transceiver Supported Protocols
|Protocol Standard||Data Rate (Gbps)|
|PCI Express Gen 1/2/3||2.5/5.0/8.0|
|JESD204||0.3125 to 12.5|
|Serial Rapid IO (SRIO)||1.25 / 2.5 / 3.125 / 5.0 / 6.25|
|Interlaken||3.125 to 10.3125|
|10Gb Ethernet XAUI, RXAUI, Double XAUI||3.125 / 6.25|
|Gigabit Ethernet (GigE)||1.25|
|CPRI||0.6144/ 1.288/ 2.4576/ 3.072/ 6.144|
|OBSAI||0.768/ 1.536 / 3.072/ 6.144|
|SDH/SONET||OC-12 @ 0.622|
OC-48 @ 2.488
OC-96 @ 4.976
|OIF-CEI-6G||4.976 to 6.375|
|Protocol Standard||Data Rate (Gbps)|
|HD-SDI||1.485 / 1.4835|
|3G-SDI||2.97 / 2.967|
|Display Port||1.62 / 2.7 / 5.4|
|SATA/SAS||1.5 / 3.0 / 6.0 /12.0|
|HyperTransport||2.4 / 2.8 / 3.2|
|Fiber Channel||1.0625 / 2.125 / 4.25|
|GPON||Upstream @ 1.244|
Downstream @ 2.488
|SPI 4.2||Min 0.622|
|Altera Serial Lite II||0.622 to 6.375|
|Xilinx Aurora (V1.2/V2.2)||Min 0.4 (V2.2)|
Min 0.6 (V1.2)
MCSC PHY Technology
BaySand’s metal configurable PHY technology provides high-speed external interface design flexibility and performance.
With features including fully configurable I/O banks with support for all I/O voltage standards, soft PHY using MCSC core cells, your design can be adapted to multiple customer and market requirements with metal only reconfiguration.
DDR PHY Features
|Interface||Half-rate (2:1) and Quarter-rate support (4:1) for DDR3/LPDDR3|
Full-rate (1:1) and half-rate (2:1) for DDR2
|Compatibility||DFI 3.1 and JEDEC standards compatibility|
|Training Features||Gate training|
Read eye centering
Duty cycle correction
CA training (LPDDR3)
|DataBus Width||8/16/32/64/72 Bits|
|Flexibility||BaySand Internal DDR controller or External controller|
|Testability||Built-in DFT Interface w/ PRBS/BIST loopback|
IEEE 1149.1 Boundary scan
Scan / ATPG
|Ease of Use||Autonomous / sequenced initialization|
Programmable output impedance and ODT
ZQ calibration of output impedance and OCT
Automatic read deskew
Integrated high-speed DLL IP
BaySand’s IP Wizard on the Web
BaySand provides Xpresso, which mimics the functionality of IP wizards commonly found in FPGA SW, to facilitate the designers ability to generate the desired IP function for the application and customization. The user interface is intuitive and similar to FPGA IP wizards for various IPs and generates all files need for implementation and verification.
- Web-based IP Generator (login required)
- No installation or HW required
- Real-time updates fro added features & support
- Generates IP to be instantiated in the user’s design
- IP modules for simulation & synthesis (Verilog)
- Instantiation example
- Automated testbench for simulation to confirm options and functionality
XpressIP Wizards Available
|Wizards Available||IP Types Generated|
|Memory||SP, TDP, SDP, SPROM, DPROM, Register File|
|Shift Register, FIFO||Shift Register w/ Taps, SCFIFO, DCFIFO|
|PLL||Reconfigurable PLL various mode|
|IO||All supported IO standards|
|Soft CDR||Soft Clock-Data-Recovery|
|PHY||DDR/DDR2/DDR3 and LVDS|
|DDR Controller||DDR2/DDR3 Controller with PHY|
|Interface||Tri-Speed Ethernet, PCI Express, XAUI, Custom SERDES PHY|