Design Flows

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Design Flows 2016-12-23T08:57:21+00:00

Overview
MCSC Foundation Technology
Design Flows
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Design Flow and Supported EDA Tools

BaySand’s technology and products utilize design flows and tools identical to traditional standard cell ASIC, ASSP and SoC design to remove the QoR risk of unconventional or internally developed in-house tools and to facilitate quick adoption and migration to customers’ design flow and methodology. Because of the MCSC technology innovation approach, 3rd party EDA tools are used in all phases of RTL to GDSII and adhere to conventional STA signoff methodology.

BaySand’s Web-based Application: Xpresso

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BaySand’s IP Wizard on the Web

BaySand provides Xpresso, which mimics the functionality of IP wizards commonly found in FPGA SW, to facilitate the designers ability to generate the desired IP function for the application and customization. The user interface is intuitive and similar to FPGA IP wizards for various IPs and generates all files need for implementation and verification.

Xpresso Features

  • Web-based IP Generator (login required)
    • No installation or HW required
    • Real-time updates fro added features & support
  • Generates IP to be instantiated in the user’s design
    • IP modules for simulation & synthesis (Verilog)
    • Instantiation example
    • Automated testbench for simulation to confirm options and functionality
BaySand's XPresso

XpressIP Wizards Available

Wizards Available IP Types Generated
Memory SP, TDP, SDP, SPROM, DPROM, Register File
Shift Register, FIFO Shift Register w/ Taps, SCFIFO, DCFIFO
PLL Reconfigurable PLL various mode
IO All supported IO standards
Soft CDR Soft Clock-Data-Recovery
PHY DDR/DDR2/DDR3 and LVDS
DDR Controller DDR2/DDR3 Controller with PHY
Interface Tri-Speed Ethernet, PCI Express, XAUI, Custom SERDES PHY