MCSC Foundation Technology
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Ultimate Silicon Customization Technology

The MCSC (Metal Configurable Standard Cell) TECHNOLOGY is patented, innovative and disruptive metal only configuration technology for ASIC or SoC with low NRE and fastest TTM advantages while providing same performance/power/area of traditional Standard Cell-based technology.

Metal-Only Configurable Technology

BaySand’s MCSC Technology offers revolutionary ways in designing your ASIC or SoC by configuring or customizing only 4 metal layers with numerous advantages as compared to existing Standard Cell-Based solutions.

The MCSC Technology Advantages

  • 4 metal layer configuration for ASIC/SoC design
  • Same power/performance/area as Standard Cell technology
  • Fastest design ECO, functional changes and derivative designs
  • Added design flexibilities and latest minute changes using MCSC Foundation Technology IPs
  • Seamless adaptation to your current ASIC design flow and methodology using 3rd party EDA SW
  • IPs for complex ASIC/SoC designs by metal-only customization
  • Fastest TTM/TTV (RTL → Engineering Sample in 7 to 10 weeks)

Same Power/Performance/Area vs. Standard Cell

The fundamental differentiation of BaySand MCSC Technology compared ASIC technologies can be shown in following table. The MCSC technology is not a Structured ASIC technology and it is more like “Super Charged Gate-Array” which has advantages Standard Cell technology while maintaining advantages of metal-only programmable technologies or FPGAs.

Fastest TTM/TTV vs Standard Cell

There is huge differentiation in Time-To-Market (TTM) using BaySand MCSC Technology compared traditional Standard Cell ASIC technology in today’s ASIC designs with many different IPs. The main design tasks in new ASIC/SoC design with 3rd party IP sourcing :

* Scroll to the right for more info
Design TasksStandard Cell ASICBaySand’s mcASIC Platform
Required IP SourcingFinding quality IPs at reasonable cost could be a big challenges and may take 2 or more monthsMost common IPs are avaiable at no cost or reasonable cost
Quality of IPs could be a big risk factor for design successIPs offered are silicon proven and characterized
Increase additional risks in integration of IPs in the designThe IPs are already part of the mcASIC Platform and integration risks are mitigated
Physical ImplementationFloorplan could take many month until design specification becomes finalFloorplan is fixed per mcASIC platform and BSI implement placement
Late minute design changes for external interface may require new floorplanNo floorplan changes required only placement changes
Power planning can be iterative process as floorplan changesRegular and repeated power distribution in platform
GDS → Engineering SampleMask generation and wafer processing for all layersWafer staged at M1 and only 4 metal masks and processing
Need package, test load-board, probe-card designAvailable and re-use for different designs
Test program development and porting to target testerAutomated test program bring up

Lowest Development Cost

MCSC Platform based technology also provide huge advantages over Standard Cell in NRE cost including mask, package, test, etc.

  • 4 Metal masks only for Design
  • Use existing package – no design or tooling
  • Use existing test board
  • Use existing probe-card
  • Streamlined test program and development