ASIC UltraShuttle MPW Program
RTL Tapeout to Working Packaged Chips in 8 Weeks
Introduction of BaySand’s Multi Project Wafer Program – ASIC UltraShuttle
With the support of a proven design flow and methodology that does not require any special EDA tools, expertise or licenses, the ASIC UltraShuttle Multi Project Wafer (MPW) program is structured to deliver high quality, verified and fully tested ASICs. The methodology is based on BaySand’s fully characterized standard cell library, coupled with proven IP and combined with BaySand’s RTL signoff design methodology that includes Design for Testability (DFT), Automatic Test Pattern Generation (ATPG), full scan, JTAG, BIST and physical implementation. The ASIC UltraShuttle MPW can also be used for FPGA to ASIC conversion minimizing risk, reducing the cost and shortening the time-to-market.
Customer Responsible to Deliver
- RTL or Netlist that includes BaySand IPs
- Customers can make use of Xpresso, featured XpressIP Wizards, to create any BaySand IPs needed. Click here to read more.
- Timing constraints
- Design review and sign off prior to Tapeout
- RTL signoff – from RTL to working packaged chips
- DFT, ATPG and BIST
- Layout and timing closure
- Production – Masks, Wafer processing, packaging and testing
- Deliver 100 units, 8 weeks from Tapeout