8 weeks to FPGA to ASIC sample delivery

Fastest Time-to-Market

for new FPGA to ASIC Conversion and future derivative designs
8 to 10 weeks for new FPGA to mcFPGA ES Sample Delivery!
Altera FPGA to BaySand mcFPGA (ASIC)
Seamless FPGA to ASIC Conversion
Drop-in Replacement for Altera/Xilinx FPGA
Package, Pin & Functional Compatible

Replace these FPGA ► mcFPGA ASIC

More than 2X Lower Unit Cost in 10 Weeks!








FPGA to ASIC Conversion

FPGA to ASIC Migration

FPGA to ASIC Replacement

HardCopy Replacement

Easypath Replacement

FPGA Volume Production



FPGA to mcFPGA Compatibility
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Unparalleled Performance • Infinite Possibilities

mcFPGA-T28C deliver breakthrough advantages in performance, power efficiency, density and system integration advantages that are unmatched in the industry. mcFPGA-T28C is the 3rd generation of the revolutionary Metal Configurable Standard Cell (MCSC) technology. The mcFPGA-T28C family of products deliver ~2x in power savings vs its 2nd generation mcFPGA-G40, let alone FPGAs.
mcFPGA-T28C offers seamless migration of both Altera and Xilinx families of FPGAs into production with the shortest TTM with just a fraction of the unit price of FGPA. mcFPGA-T28C features unprecedented performance improvement and increase in chip resources and density versus the industry leading predecessor mcFPGA-G40L, leaving the power hungry and low density FPGA further behind.


Think mcFPGA-T28C : Your Best Choice for FPGA replacement & Production

You’ll discover the mcFPGA-T28C delivers breakthrough advantages over various Altera and Xilinx FPGA families. Leveraging benefits and proven transceiver and memory interface technology while further enhancing the feature sets, mcFPGA-T28C family provides an unprecedented level of system bandwidth with complexity. Key benefits include:

  • Technology : TSMC 28nm HPC
  • TTM : 7~ 10 Weeks (RTL to Engineering Sample)
  • Up to 75M Usable Gates (Std. Cell ASIC Gates)
  • Up to 1500 I/Os : All IO standards for (1.2v – 3.3v)
  • Up to 138 Mbits MCSC Block RAMs (mcBRAM)
  • Up to 120 channels of Multi-Protocol Transceiver (12.5 Gbps)
  • Multi-Protocol PCS (Optimized per Protocol)
  • Improved DDR3 performance up to 2.133 Gbps
  • New DDR4/LPDDR4 supports up to 3.2Gbps
  • 3.2 GHz PLL, 2x clock rate improvement against predecessor for multiple clock generations
  • 1.6 Gbps LVDS performance
  • Unlimited & Flexible Clock Scheme
  • Seamless FPGA to mcFPGA migration with ease

* Performance and numbers information for mcFPGA-T28C is preliminary and subject to change


mcFPGA-T28C Foundation Technology Features

  • MCSC Core (mcCORE) :
    • 12-grid MCSC standard cells
    • Low Power Design – Power Gating, Island supported
    • 500+ cells with multiple drives and functions
    • Multi-Vt Support for performance/power optimization
  • MCSC Memory:
    • 10K DP Block RAMs
    • 20K SP Block RAMs
    • Register File for small or wide memories (FPGA Distributed RAM equivalent)
    • Functionality and feature are super-set of both Altera and Xilinx Memories
  • MCSC IO (mcMPIO)
    • MPIO => Multi-Standard I/Os (1.2v – 3.3v) : supports all I/O standards
    • Supported IO standards:
      • Low speed LVCMOS, LVTTL 1.5V to 3.3V
      • Memory interface HSUL 1.2V, SSTL 1.2V to 2.5V, HSTL 1.5V to 1.8V
      • Differential I/O LVDS 2.5V
      • On-chips termination (static and dynamic)
    • 3.2GHz PLL with SSC Generation
    • Low Jitter Perfromance
    • 9 Different Outputs per PLL with different frequency & phase
    • Supports spread spectrum input clock and PLL re-configuration
  • MCSC Transceiver
    • CDR based PMA at 12.5Gbps with multi-protocol support
    • Synthesizable and optimizable PCS per desired protocol
    • Flexible placement and assignment
    • LVDS PHY supports up to x16 serializer/deserializer (SERDES), dynamic phase alignment (DPA), and soft-CDR circuitry
    • DDR3/DDR4/LPDDR4 phy supports read/write leveling, on chip termination and calibration, half/quarter rate
  • Full Package Compatibility for FPGAs

Device Family Table

mcFPGA-T28C : Your Best Choice for FPGA Replacement & Production

mcFPGA-G40L devices with 12.5Gbps transceivers : Up to 75 Million Standard-Cell ASIC usable gates and 120 full-duplex clock data recovery (CDR)-based transceivers at up to 12.5Gbps

Find your mcFPGA device mapping for your current FPGAs>>

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DeviceUsable Gate (M)M10KMemory (K)PLLIOTran CH