8 weeks to FPGA to ASIC sample delivery

Fastest Time-to-Market

for new FPGA to ASIC Conversion and future derivative designs
8 to 10 weeks for new FPGA to mcFPGA ES Sample Delivery!
Altera FPGA to BaySand mcFPGA (ASIC)
Seamless FPGA to ASIC Conversion
Drop-in Replacement for Altera/Xilinx FPGA
Package, Pin & Functional Compatible
mcFPGA ASIC

Replace these FPGA ► mcFPGA ASIC

More than 2X Lower Unit Cost in 10 Weeks!

Stratix

Virtex

Cyclone

Kintex

Arria

Artix

Spartan

FPGA to ASIC Conversion

FPGA to ASIC Migration

FPGA to ASIC Replacement

HardCopy Replacement

Easypath Replacement

FPGA Volume Production

FPGA vs. ASIC

mcFPGA

Overview
FPGA to mcFPGA Compatibility
Device Family
Device Mapper
Ask Us

mcFPGA-G65L

mcFPGA-G65L

Unmatched TTM Volume Production Solution for Your Cost-Sensitive Design

mcFPGA-G65L delivers unparalleled unit cost advantage for volume production, and yet provides shortest TTM. Featuring the revolutionary Metal Configurable Standard Cell (MCSC) technology, the mcFPGA-G65L family of products deliver more than 2x in power savings and unit price.
mcFPGA-G65L family also provides package and pin compatibility with Altera or Xilinx FPGAs, meaning no board change required and seamless FPGA → mcFPGA migration.

Overview

Think mcFPGA-G65L : Your Best Choice for FPGA Replacement & Volume Production

You’ll discover the mcFPGA-G65L delivers breakthrough advantages over various Altera and Xilinx FPGA families. Leveraging benefits and proven transceiver and memory interface technology, mcFPGA-G65L family provides an unprecedented level of system bandwidth with complexity. Key benefits include:

  • Technology : GF 65nm LP
  • TTM : 7~ 10 Weeks (RTL to Engineering Sample)
  • Up to 21M Usable Gates (Std. Cell ASIC Gates)
  • Up to 1250 I/Os : All IO standards for (1.2v – 3.3v)
  • Up to 23Mbits MCSC Block RAMs (mcBRAM)
  • Up to 25 channels of Multi-Protocol Transceiver (6.5 Gbps)
  • Multi-Protocol PCS (Optimized per Protocol)
  • Up to 1066 Gbps DDR3 performance
  • 1.6 GHz PLL for multiple clock generations
  • Up to 1.6 Gbps LVDS performance
  • Unlimited & Flexible Clock Scheme
  • Seamless FPGA to mcFPGA migration with ease

Features

mcFPGA-G65L Foundation Technology Features

  • MCSC Core (mcCORE) :
    • 12-grid MCSC standard cells
    • Low Power Design – Power Gating, Island supported
    • 500+ cells with multiple drives and functions
    • Multi-Vt Support for performance/power optimization
  • MCSC Memory:
    • M9Kb Block RAMs supporting single port (SP), simple dual port (SDP) and true dual port (TDP)
    • Register File for small or wide memories (FPGA Distributed RAM equivalent)
    • Functionality and feature are super-set of both Altera and Xilinx Memories
  • MCSC IO (mcMPIO)
    • MPIO => Multi-Standard I/Os (1.5v – 3.3v) : supports all I/O standards
    • Supported IO standards:
      • low speed LVCMOS, LVTTL 1.5V to 3.3V
      • Memory interface SSTL 1.5V to 2.5V, HSTL 1.5V to 1.8V
      • Differential I/O LVDS 2.5V
      • On-chips termination (static and dynamic)
  • MCSC PLL
    • 1.6GHz PLL
    • 6 Different Outputs per PLL with different frequency & phase
    • Supports spread spectrum input clock and PLL re-configuration
  • MCSC Transceiver
    • 6.5Gbps Multi-Protocol support
    • Synthesizable and optimizable PCS per desired protocol
  • MCSC DDR/LVDS PHY
    • Flexible placement and assignment
    • LVDS PHY supports serializer/deserializer (SERDES), dynamic phase alignment (DPA), and soft-CDR circuitry
    • DDR phy supports read/write leveling, on chip termination and calibration, half/quarter rate
  • Full Package Compatibility for FPGAs

Device Family Table

mcFPGA-G65L : Your Best Choice for FPGA Replacement & Production

The mcFPGA-65L family include two device variants:

  • mcFGPA-G65L devices without transceivers : Upto 21 Million Standard-Cell ASIC usable gates and 23M bits of metal configurable Block Rams(mcBRAMs)
  • mcFPGA-65LS devices with 6.5Gbps transceivers : Upto 15 Million Standard-Cell ASIC usable gates and 20 full-duplex clock data recovery (CDR)-based transceivers at up to 6.5Gbps

Find your mcFPGA device mapping for your current FPGAs>>

* Scroll to the right for more info.
Device Usable Gate (M) M9K Memory (K) PLL IO Tran CH
mcFG65L-10 2.0 216 1,991 6 362
mcFG65L-20 4.0 486 4,479 8 556
mcFG65L-30 6.0 1,098 10,119 12 779
mcFG65L-40 16.0 2,080 19,169 12 1,110
mcFG65L-50 21.0 2,560 23,593 20 1,218
mcFG65L-60 21.0 4,480 41,288 28 1,250
mcFG65L-10S  4.0 496 4,571 6 490 10
mcFG65L-20S 7.0 936 8,626 8 610 15
mcFG65L-30S 15.0 1,640 15,114 10 744 20
mcFG65L-40S 20.0 2,000 18,000 12 850 25
  1. Actual usable ASIC gates
  2. 6.5 Gbps Multi-Protocol Transceiver