8 weeks to FPGA to ASIC sample delivery

Fastest Time-to-Market

for new FPGA to ASIC Conversion and future derivative designs
8 to 10 weeks for new FPGA to mcFPGA ES Sample Delivery!
Altera FPGA to BaySand mcFPGA (ASIC)
Seamless FPGA to ASIC Conversion
Drop-in Replacement for Altera/Xilinx FPGA
Package, Pin & Functional Compatible

Replace these FPGA ► mcFPGA ASIC

More than 2X Lower Unit Cost in 10 Weeks!








FPGA to ASIC Conversion

FPGA to ASIC Migration

FPGA to ASIC Replacement

HardCopy Replacement

Easypath Replacement

FPGA Volume Production



FPGA to mcFPGA Compatibility
Device Family
Device Mapper
Ask Us

Seamless FPGA to ASIC Conversion & Volume Production Solution

The mcFPGA products are comprehensive multiple process node mcPLATFORM specially tailored to enable seamless migration from Altera or Xilinx FPGA (such as Stratix/Cyclone/Arria & Virtex/Kintex/Artix/Spartan) designs to BaySand’s ASIC.
BaySand currently offers mcFPGA Platform Solutions in 65nm to advanced 28nm process technology with fastest time-to-market (TTM) and optimized unit cost (ASP) compared to any other existing solutions. BaySand provides families of mcFPGA products and numerous IPs to help our customers to differentiate their products from the competitions by enabling fast system development with FPGAs and seamless migration to mcFPGA solution for best in price/performance/power.

FPGA Volume Production Utilizing MCSC Platform Technology

The mcFPGA products are architected ground-up to enable seamless FPGA to ASIC conversion from Altera or Xilinx FPGA designs to BaySand’s MCSC platform solution (mcFPGA). The mcFPGA not only provides seamless FPGA to ASIC migration but also superior Standard Cell ASIC-like Power, Performance & ASP advantages.

The mcFPGA products & solutions provides following benefits for FPGA to ASIC migration:

  • FPGA Pin-compatibility or optimized package offerings(for lower ASP)
  • Guaranteed functional compatibility
  • Enhanced or same Performance compatibility
  • IP compatibility for minimum or no FPGA RTL changes
  • Robust design flow and methodology for 1st time silicon success

Lowest Power Consumption (Upto 10X power reduction vs. FPGA)

Power is becoming the primary concern for most FPGA designs. Beyond meeting thermal constraints, lowering power improves system cost and reliability, and supports increased performance.
By leveraging power advantage of MCSC Technology (inherent ASIC like power advantage), mcFPGA can achieve up to 10X power reduction compared to FPGAs by lowering both static and dynamic power consumption.

Performance – Benchmark Design #1

VendorDeviceTotal PowerRatio
AlteraStratix 3342116.4
Cyclone 416487.9
Arria 417958.6
Stratix 517658.5
XilinxVirtex 6324115.5
Artix 711305.4
Kintex 711675.6

Breakthrough FPGA Performance Limits

Building on the MCSC logic architecture and technology, mcFPGA families enable much higher performance compared to FPGAs which may even be one or two process technology nodes ahead.
Based on many FPGA design to ASIC migration examples, we can consistently achieve easy migration in terms of performance to mcF65L (65nm) or mcF40L (40nm) devices from 28nm FPGA devices. See our device mapper for more detail.

Performance – Benchmark Design #2

VendorDeviceMax. Freq. (MHz)Ratio
Cyclone 5-E230-38%
Cyclone 5-GX233-37%
Arria 5282-24%
Stratix 5306-17%
Kintex 7230-38%
Virtex 7240-35%

ASIC-like Unit Price : Lowest ASP

BaySand mcFPGA and IPs provide upto 10X lower ASP in volume production compare to FPGAs. The MCSC technology, used for mcFPGA product, offers comparable or similar die size compared to Standard-Cell ASIC. Therefore customers can enjoy the benefits of seamless migration methodology and smallest die size (lower ASP) by taking advantage of mcFPGA.

The Fastest TTM from FPGAs

The MCSC metal only programmable technology shortens time to market (TTM) for FPGA to ASIC migration and future design changes or new derivative designs.
The mcFPGA wafers are stored at M1 and only a few metal layers are processed to accommodate different designs with fast TTM advantages.

FPGA to mcFPGA ES Sample Delivery
TasksDuration (Week)
FPGA IP Migration1
RTL to TapeOut2 ~ 4
ES Delivery5
Total8 ~ 10

mcFPGA vs. FPGA (Power/Performance/Price) Explained

The qualitative explanation of why mcFPGA products using MCSC technology have unparalleled power/performance/price advantages.


  • LUT + Register Based Logic Fabric
  • Large Insertion Delay
  • Unused Circuit MUST be powered
  • Unused Circuit → Larger Die Area
  • QoR based on FPGA SW

FPGA Routing Structure

  • Segmented Routing with Active Switches + Buffer
  • Very Large Routing Delays
  • Routing Area – upto 70% of Core Area
  • Most of critical path delay could be routing related
  • Always On Routing (even not used)
  • Fixed Clock Tree to All Registers

MCSC Logic

  • Min. Transistors Logic (ASIC-like)
  • ASIC like Logic Cells → Small
  • Only Used Logic is Powered ON
  • Unused BC are off → NO Static Power
  • Same Area, Performance as ASIC

MCSC Routing

  • 4 Metal Layer Routing
  • ASIC-like Optimum Metal Routing
  • Clock Tree per design need
  • ASIC P&R Tools & Methodology
  • 5X to 16X Lower Power
  • 2X to 5X Better Performance



BaySand’s IP Wizard on the Web

BaySand provides Xpresso, which mimics the functionality of IP wizards commonly found in FPGA SW, to facilitate the designers ability to generate the desired IP function for the application and customization. The user interface is intuitive and similar to FPGA IP wizards for various IPs and generates all files need for implementation and verification.

Xpresso Features

  • Web-based IP Generator (login required)
    • No installation or HW required
    • Real-time updates fro added features & support
  • Generates IP to be instantiated in the user’s design
    • IP modules for simulation & synthesis (Verilog)
    • Instantiation example
    • Automated testbench for simulation to confirm options and functionality
BaySand's XPresso

XpressIP Wizards Available

Wizards AvailableIP Types Generated
MemorySP, TDP, SDP, SPROM, DPROM, Register File
Shift Register, FIFOShift Register w/ Taps, SCFIFO, DCFIFO
PLLReconfigurable PLL various mode
IOAll supported IO standards
Soft CDRSoft Clock-Data-Recovery
DDR ControllerDDR2/DDR3 Controller with PHY
InterfaceTri-Speed Ethernet, PCI Express, XAUI, Custom SERDES PHY