Package, Pin & Functional Compatible
FPGA to ASIC Conversion
FPGA to ASIC Migration
FPGA to ASIC Replacement
FPGA Volume Production
FPGA vs. ASIC
Seamless FPGA to ASIC Conversion & Volume Production Solution
The mcFPGA products are comprehensive multiple process node mcPLATFORM specially tailored to enable seamless migration from Altera or Xilinx FPGA (such as Stratix/Cyclone/Arria & Virtex/Kintex/Artix/Spartan) designs to BaySand’s ASIC.
BaySand currently offers mcFPGA Platform Solutions in 65nm to advanced 28nm process technology with fastest time-to-market (TTM) and optimized unit cost (ASP) compared to any other existing solutions. BaySand provides families of mcFPGA products and numerous IPs to help our customers to differentiate their products from the competitions by enabling fast system development with FPGAs and seamless migration to mcFPGA solution for best in price/performance/power.
FPGA Volume Production Utilizing MCSC Platform Technology
The mcFPGA products are architected ground-up to enable seamless FPGA to ASIC conversion from Altera or Xilinx FPGA designs to BaySand’s MCSC platform solution (mcFPGA). The mcFPGA not only provides seamless FPGA to ASIC migration but also superior Standard Cell ASIC-like Power, Performance & ASP advantages.
The mcFPGA products & solutions provides following benefits for FPGA to ASIC migration:
- FPGA Pin-compatibility or optimized package offerings(for lower ASP)
- Guaranteed functional compatibility
- Enhanced or same Performance compatibility
- IP compatibility for minimum or no FPGA RTL changes
- Robust design flow and methodology for 1st time silicon success
Lowest Power Consumption (Upto 10X power reduction vs. FPGA)
Power is becoming the primary concern for most FPGA designs. Beyond meeting thermal constraints, lowering power improves system cost and reliability, and supports increased performance.
By leveraging power advantage of MCSC Technology (inherent ASIC like power advantage), mcFPGA can achieve up to 10X power reduction compared to FPGAs by lowering both static and dynamic power consumption.
Performance – Benchmark Design #1
Breakthrough FPGA Performance Limits
Building on the MCSC logic architecture and technology, mcFPGA families enable much higher performance compared to FPGAs which may even be one or two process technology nodes ahead.
Based on many FPGA design to ASIC migration examples, we can consistently achieve easy migration in terms of performance to mcF65L (65nm) or mcF40L (40nm) devices from 28nm FPGA devices. See our device mapper for more detail.
Performance – Benchmark Design #2
|Vendor||Device||Max. Freq. (MHz)||Ratio|
ASIC-like Unit Price : Lowest ASP
BaySand mcFPGA and IPs provide upto 10X lower ASP in volume production compare to FPGAs. The MCSC technology, used for mcFPGA product, offers comparable or similar die size compared to Standard-Cell ASIC. Therefore customers can enjoy the benefits of seamless migration methodology and smallest die size (lower ASP) by taking advantage of mcFPGA.
The Fastest TTM from FPGAs
The MCSC metal only programmable technology shortens time to market (TTM) for FPGA to ASIC migration and future design changes or new derivative designs.
The mcFPGA wafers are stored at M1 and only a few metal layers are processed to accommodate different designs with fast TTM advantages.
|FPGA to mcFPGA ES Sample Delivery|
|FPGA IP Migration||1|
|RTL to TapeOut||2 ~ 4|
|Total||8 ~ 10|
mcFPGA vs. FPGA (Power/Performance/Price) Explained
The qualitative explanation of why mcFPGA products using MCSC technology have unparalleled power/performance/price advantages.
FPGA Routing Structure
BaySand’s IP Wizard on the Web
BaySand provides Xpresso, which mimics the functionality of IP wizards commonly found in FPGA SW, to facilitate the designers ability to generate the desired IP function for the application and customization. The user interface is intuitive and similar to FPGA IP wizards for various IPs and generates all files need for implementation and verification.
- Web-based IP Generator (login required)
- No installation or HW required
- Real-time updates fro added features & support
- Generates IP to be instantiated in the user’s design
- IP modules for simulation & synthesis (Verilog)
- Instantiation example
- Automated testbench for simulation to confirm options and functionality
XpressIP Wizards Available
|Wizards Available||IP Types Generated|
|Memory||SP, TDP, SDP, SPROM, DPROM, Register File|
|Shift Register, FIFO||Shift Register w/ Taps, SCFIFO, DCFIFO|
|PLL||Reconfigurable PLL various mode|
|IO||All supported IO standards|
|Soft CDR||Soft Clock-Data-Recovery|
|PHY||DDR/DDR2/DDR3 and LVDS|
|DDR Controller||DDR2/DDR3 Controller with PHY|
|Interface||Tri-Speed Ethernet, PCI Express, XAUI, Custom SERDES PHY|