8 weeks to FPGA to ASIC sample delivery

Fastest Time-to-Market

for new FPGA to ASIC Conversion and future derivative designs
8 to 10 weeks for new FPGA to mcFPGA ES Sample Delivery!
Altera FPGA to BaySand mcFPGA (ASIC)
Seamless FPGA to ASIC Conversion
Drop-in Replacement for Altera/Xilinx FPGA
Package, Pin & Functional Compatible
mcFPGA ASIC

Replace these FPGA ► mcFPGA ASIC

More than 2X Lower Unit Cost in 10 Weeks!

Stratix

Virtex

Cyclone

Kintex

Arria

Artix

Spartan

FPGA to ASIC Conversion

FPGA to ASIC Migration

FPGA to ASIC Replacement

HardCopy Replacement

Easypath Replacement

FPGA Volume Production

FPGA vs. ASIC

mcFPGA

Overview
FPGA to mcFPGA Compatibility
Device Family
Device Mapper
Ask Us

Seamless FPGA to ASIC Conversion & Volume Production Solution

The mcFPGA products are comprehensive multiple process node mcPLATFORM specially tailored to enable seamless migration from Altera or Xilinx FPGA (such as Stratix/Cyclone/Arria & Virtex/Kintex/Artix/Spartan) designs to BaySand’s ASIC.
BaySand currently offers mcFPGA Platform Solutions in 65nm to advanced 28nm process technology with fastest time-to-market (TTM) and optimized unit cost (ASP) compared to any other existing solutions. BaySand provides families of mcFPGA products and numerous IPs to help our customers to differentiate their products from the competitions by enabling fast system development with FPGAs and seamless migration to mcFPGA solution for best in price/performance/power.

FPGA Volume Production Utilizing MCSC Platform Technology

The mcFPGA products are architected ground-up to enable seamless FPGA to ASIC conversion from Altera or Xilinx FPGA designs to BaySand’s MCSC platform solution (mcFPGA). The mcFPGA not only provides seamless FPGA to ASIC migration but also superior Standard Cell ASIC-like Power, Performance & ASP advantages.

The mcFPGA products & solutions provides following benefits for FPGA to ASIC migration:

  • FPGA Pin-compatibility or optimized package offerings(for lower ASP)
  • Guaranteed functional compatibility
  • Enhanced or same Performance compatibility
  • IP compatibility for minimum or no FPGA RTL changes
  • Robust design flow and methodology for 1st time silicon success

Lowest Power Consumption (Upto 10X power reduction vs. FPGA)

Power is becoming the primary concern for most FPGA designs. Beyond meeting thermal constraints, lowering power improves system cost and reliability, and supports increased performance.
By leveraging power advantage of MCSC Technology (inherent ASIC like power advantage), mcFPGA can achieve up to 10X power reduction compared to FPGAs by lowering both static and dynamic power consumption.

Performance – Benchmark Design #1

Vendor Device Total Power Ratio
Altera Stratix 3 3421 16.4
Cyclone 4 1648 7.9
Arria 4 1795 8.6
Stratix 5 1765 8.5
Xilinx Virtex 6 3241 15.5
Artix 7 1130 5.4
Kintex 7 1167 5.6
BaySand mcF65L-10 209 1.0

Breakthrough FPGA Performance Limits

Building on the MCSC logic architecture and technology, mcFPGA families enable much higher performance compared to FPGAs which may even be one or two process technology nodes ahead.
Based on many FPGA design to ASIC migration examples, we can consistently achieve easy migration in terms of performance to mcF65L (65nm) or mcF40L (40nm) devices from 28nm FPGA devices. See our device mapper for more detail.

Performance – Benchmark Design #2

Vendor Device Max. Freq. (MHz) Ratio
Altera
(28nm)
Cyclone 5-E 230 -38%
Cyclone 5-GX 233 -37%
Arria 5 282 -24%
Stratix 5 306 -17%
Xilinx
(28nm)
Kintex 7 230 -38%
Virtex 7 240 -35%
BaySand mcF40L 440 19%
mcF65L 370 0%

ASIC-like Unit Price : Lowest ASP

BaySand mcFPGA and IPs provide upto 10X lower ASP in volume production compare to FPGAs. The MCSC technology, used for mcFPGA product, offers comparable or similar die size compared to Standard-Cell ASIC. Therefore customers can enjoy the benefits of seamless migration methodology and smallest die size (lower ASP) by taking advantage of mcFPGA.

The Fastest TTM from FPGAs

The MCSC metal only programmable technology shortens time to market (TTM) for FPGA to ASIC migration and future design changes or new derivative designs.
The mcFPGA wafers are stored at M1 and only a few metal layers are processed to accommodate different designs with fast TTM advantages.

FPGA to mcFPGA ES Sample Delivery
Tasks Duration (Week)
FPGA IP Migration 1
RTL to TapeOut 2 ~ 4
ES Delivery 5
Total 8 ~ 10

mcFPGA vs. FPGA (Power/Performance/Price) Explained

The qualitative explanation of why mcFPGA products using MCSC technology have unparalleled power/performance/price advantages.

FPGA LC

  • LUT + Register Based Logic Fabric
  • Large Insertion Delay
  • Unused Circuit MUST be powered
  • Unused Circuit → Larger Die Area
  • QoR based on FPGA SW

FPGA Routing Structure

  • Segmented Routing with Active Switches + Buffer
  • Very Large Routing Delays
  • Routing Area – upto 70% of Core Area
  • Most of critical path delay could be routing related
  • Always On Routing (even not used)
  • Fixed Clock Tree to All Registers

MCSC Logic

  • Min. Transistors Logic (ASIC-like)
  • ASIC like Logic Cells → Small
  • Only Used Logic is Powered ON
  • Unused BC are off → NO Static Power
  • Same Area, Performance as ASIC

MCSC Routing

  • 4 Metal Layer Routing
  • ASIC-like Optimum Metal Routing
  • Clock Tree per design need
  • ASIC P&R Tools & Methodology
  • 5X to 16X Lower Power
  • 2X to 5X Better Performance

xpresso_decoder

xpresso_decoder

BaySand’s IP Wizard on the Web

BaySand provides Xpresso, which mimics the functionality of IP wizards commonly found in FPGA SW, to facilitate the designers ability to generate the desired IP function for the application and customization. The user interface is intuitive and similar to FPGA IP wizards for various IPs and generates all files need for implementation and verification.

Xpresso Features

  • Web-based IP Generator (login required)
    • No installation or HW required
    • Real-time updates fro added features & support
  • Generates IP to be instantiated in the user’s design
    • IP modules for simulation & synthesis (Verilog)
    • Instantiation example
    • Automated testbench for simulation to confirm options and functionality
BaySand's XPresso

XpressIP Wizards Available

Wizards Available IP Types Generated
Memory SP, TDP, SDP, SPROM, DPROM, Register File
Shift Register, FIFO Shift Register w/ Taps, SCFIFO, DCFIFO
PLL Reconfigurable PLL various mode
IO All supported IO standards
Soft CDR Soft Clock-Data-Recovery
PHY DDR/DDR2/DDR3 and LVDS
DDR Controller DDR2/DDR3 Controller with PHY
Interface Tri-Speed Ethernet, PCI Express, XAUI, Custom SERDES PHY

FPGA-to-ASIC Conversion

ON Semiconductor is the industry leader specializing in converting FPGAs to ASICs. We provide significant cost savings, performance enhancement, and product assurance. Our customers have been able to reduce system costs considerably by successfully substituting their high cost FPGAs with drop-in ASIC replacements in over 4,000 applications. In most cases, higher performance, lower power and better thermal performance can be achieved in the ASIC. ON Semiconductor provides a parallel development path for FPGA development. This leverages the inherent flexibility of an FPGA during the development phase while accelerating the path to low-cost production with an ASIC.

We offer competitive design cycle times allowing for a quick ramp to production and reduced cost. We also maintain manufacturing processes for over long periods of time insuring an uninterrupted part supply.

 

Features

Benefits

Smaller Die Size Drives Lower Cost

FPGAs use leading edge technologies in order to obtain the same system performance as an ASIC does in older technologies. A design implemented in an FPGA will have a larger die size due to their architecture, fabric and due to the programmable logic and interconnect overhead. This not only increases the overall power used in the FPGA but it has a direct effect on the cost. For the same amount of gates and RAM an ASIC has a much smaller die size and usually requires fewer levels of metal. This is due to more efficient custom routing used in an ASIC.

The smaller die size, fewer processing steps and older generation of technology are the main cost advantages for the ASIC. By taking advantage of the superior density offered by an ASIC and possibly combining several FPGAs onto a single chip, additional benefits can be realized: reduced board size, smaller BOM, improved power consumption and maximized cost savings.

Customization Drives Higher Performance

As device speeds increase, FPGAs experience a dramatic increase in power consumption over an ASIC design. This is largely due to how FPGAs are routed. An FPGA cannot be directly routed from point A to point B on a chip. Instead a signal must be routed through many programmable routing switches and wire segments, each with considerable capacitive overhead which causes an increase in power consumption. In addition, clocks are routed with predefined clock network across the entire die with oversized drivers to handle all potential clocking requirements. This large clock network has a sizeable capacitive load and will draw a substantial amount of power at higher frequencies.

In the ASIC, clock drivers and networks are tailored to the specific clock network requirements and routed efficiently in metal layers. There is essentially no unused logic in ASICs drawing power. High-end FPGA technology uses smaller geometry technology than ASICs while using the same core voltage. The combination of advanced geometry technologies and same core voltage as the ASIC results in more leakage adding to the higher power usage in FPGAs. The reduction in power usage by an ASIC allows the use of less complex packages, again helping reduce the overall cost of the product as package costs can be a third or more of the device cost.

Why Convert?

We have successfully converted thousands of designs from costly FPGAs to efficient ASICs throughout the past few decades. The lower unit cost of an ASIC has long been a key motivating factor in such conversions. However, the appeal of FPGA to ASIC conversions goes far beyond the cost savings. The significant power savings realized through using an ASIC in the place of an FPGA significantly increases battery life. Applications, such as hand-held devices, find this to be a tremendous advantage. In contrast to the programmable logic used in FPGAs, the hard-coding of the logic in an ASIC, does not allow reprogramming of the device, thereby increasing security and reliability. This added reliability makes ASICs the obvious choice for flight-critical applications where SRAM based FPGAs are typically not qualified.