MCSC ASIC Solution
Fast TMM, Low Risk, Low NRE ASIC Solution
Overview
For the optimum solution for your application, BaySand offers full customization services enabling you to define your own device features in terms of functionality, logic gates, I/Os, memories etc. based on the requirements and specifications of your application. With the ability to combine your custom/proprietary IP with BaySand’s rich portfolio of metal configurable MCSC IPs and functional IP blocks available across a suite of process technologies and foundry partners, mcASIC delivers equal or better area density, power and performance compared to Standard Cell.
In addition, mcASIC offers significant benefits for design ECOs, derivative applications and customization with the fastest time to market and reduced design and tooling costs.
Providing your RTL design to BaySand, we can implement your design with all the advantages of our MCSC technology including full manufacturing services.
Contact your local BaySand Sales Representative to learn how BaySand can be your partner in advanced ASIC success.
ASIC Design with BaySand
BaySand focuses on providing our customers with the best ASIC design support model from start to finish by leveraging tailored and customized web based solutions. Customers get 24 x 7 support from BaySand . Projects are managed and monitored by our Project Management System (PM) to keep you on top of your project and on schedule.
We believe the project management system, which is visible to customer, is key to successfully manage and monitor the progress and issues to results in customer satisfaction and successful execution and delivery.
Click here to read more about Xpresso, featured XpressIP Wizards, our intuitive approach for IP and testbench generation .
ASIC Design Engagement Models
Flexible and Customer Centric
BaySand provides customer focused ASIC , ASSP and SoC design engagement models to accommodate customers design requirements and controllability. Customers have full control of the design engagement for differentiation and time to market by leveraging resources, schedule and expertise of the device implementation.
Device Family Table
| MCSC Foundation Technology |
Device Family | Transceiver | Max. Usable Gates (M) |
SRAM | Max. IO | Max. Transceiver | |
|---|---|---|---|---|---|---|---|
| M9/10K | Mbit | ||||||
| MCSC-G40L | mcAG40L-XXS | 12.5 Gbps | 40 | 7,000 | 70 | 1,250 | 96 |
| MCSC-G65L | mcAG65L-XX | – | 21 | 4,480 | 40 | 1,250 | – |
| mcAG65L-XXS | 6.5 Gbps | 20 | 2,000 | 18 | 850 | 25 | |
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BaySand’s IP Wizard on the WebBaySand provides Xpresso, which mimics the functionality of IP wizards commonly found in FPGA SW, to facilitate the designers ability to generate the desired IP function for the application and customization. The user interface is intuitive and similar to FPGA IP wizards for various IPs and generates all files need for implementation and verification. |
Xpresso Features
- Web-based IP Generator (login required)
- No installation or HW required
- Real-time updates fro added features & support
- Generates IP to be instantiated in the user’s design
- IP modules for simulation & synthesis (Verilog)
- Instantiation example
- Automated testbench for simulation to confirm options and functionality
XpressIP Wizards Available
| Wizards Available | IP Types Generated |
|---|---|
| Memory | SP, TDP, SDP, SPROM, DPROM, Register File |
| Shift Register, FIFO | Shift Register w/ Taps, SCFIFO, DCFIFO |
| PLL | Reconfigurable PLL various mode |
| IO | All supported IO standards |
| Soft CDR | Soft Clock-Data-Recovery |
| PHY | DDR/DDR2/DDR3 and LVDS |
| DDR Controller | DDR2/DDR3 Controller with PHY |
| Interface | Tri-Speed Ethernet, PCI Express, XAUI, Custom SERDES PHY |