BaySand ASIC Program
RTL Tapeout to Working Packaged Chips in 8 Weeks
|Available ASIC Technologies||MCSC-G65L||MCSC-G40L||Fujitsu/UMC||SMIC||TSMC|
|Process Technology||65nm (LP)||40nm (LP)||90 – 40nm||110 – 40nm||28 – 7nm|
Introduction of BaySand’s ASIC Program
With the use of a proven design flow and our state of the art tools, BaySand methodology does not require of our customers any special EDA tools, expertise or licenses. BaySand ASIC program is structured to deliver high quality, verified, and fully tested ASICs. The methodology is based on BaySand’s fully characterized standard cell library, coupled with proven IP and combined with BaySand’s RTL signoff design methodology that includes Design for Testability (DFT), Automatic Test Pattern Generation (ATPG), full scan, JTAG, BIST and physical implementation. We also provide FPGA to ASIC conversion services, while minimizing risk, reducing the cost and shortening the time-to-market.
Customer Responsible for the Delivery of:
- RTL or Netlist that includes BaySand IPs
- Customers can make use of Xpresso, featured XpressIP Wizards, to create any BaySand IPs needed. Click here to read more.
- Timing constraints
- Design review and sign off prior to Tapeout
- RTL signoff – from RTL to working packaged chips
- DFT, ATPG and BIST
- Layout and timing closure
- Production – Masks, Wafer processing, packaging and testing
- Deliver 100 units, 8 weeks from Tapeout