ASIC UltraShuttle MPW

BaySand ASIC Program

RTL Tapeout to Working Packaged Chips in 8 Weeks

Contact Us
Contact Us
Available ASIC TechnologiesMCSC-G65LMCSC-G40LFujitsu/UMCSMICTSMC
Process Technology65nm (LP)40nm (LP)90 – 40nm110 – 40nm28 – 7nm

Introduction of BaySand’s ASIC Program

With the use of a proven design flow and our state of the art tools, BaySand methodology does not require of our customers any special EDA tools, expertise or licenses. BaySand ASIC program is structured to deliver high quality, verified, and fully tested ASICs. The methodology is based on BaySand’s fully characterized standard cell library, coupled with proven IP and combined with BaySand’s RTL signoff design methodology that includes Design for Testability (DFT), Automatic Test Pattern Generation (ATPG), full scan, JTAG, BIST and physical implementation. We also provide FPGA to ASIC conversion services, while minimizing risk, reducing the cost and shortening the time-to-market.

Customer Responsible for the Delivery of:

  1. RTL or Netlist that includes BaySand IPs
    • Customers can make use of Xpresso, featured XpressIP Wizards, to create any BaySand IPs needed. Click here to read more.
  2. Timing constraints
  3. Design review and sign off prior to Tapeout

BaySand Responsibility

  1. RTL signoff – from RTL to working packaged chips
    1. Synthesis
    2. DFT, ATPG and BIST
    3. Layout and timing closure
  2. Production – Masks, Wafer processing, packaging and testing
  3. Deliver 100 units, 8 weeks from Tapeout
Customer to BaySand interaction on MPW project

Compared to classic silicon shuttle (MPW), BaySand’s ASIC Program delivers the following benefits:

* Scroll to the right to see more info
BaySand’s ASIC UltraShuttle Advantages
RTL Signoff
  • State of the art methodology and design flow
  • Saves the customer access to EDA tools
  • Saves the need for EDA tools expertise
  • Support from experts in timing closure
  • Professional DFT, ATPG and BIST support
  • BaySand takes ownership on the tapeout process
  • Enables easy FPGA conversion
Delivery of packaged and fully tested parts
  • Packaging and testing done by world class providers
  • Additional quality service at no extra charge
  • Customer can focus on testing the design
  • Production ready testing in case the design goes to production
Access to IP blocks provided
  • PLL, RAM cells, special IOs and other IP blocks available at no extra charge
  • IP partners IP available to customers
  • Proven and tested IP
Low cost – design in shared among multiple designs
  • Low risk
  • Easy access to real silicon
Quick Turnaround time – 8 weeks from tapeout
  • Saves times during the validation process
  • Lower the Time to Market (TTM) time and risk

Production Ready Design – BaySand can support Volume Production!

BaySand ASIC Program VS Traditional Multi Project Wafer Program

* Scroll to the right to see more info
BaySand ASIC ProgramTraditional foundry shuttle service
RTL hand off and sign offVSGDS hand off
Customer does not need special tools, licenses, or EDA tools expertiseEDA tools and EDA tools expertise required
BaySand ASIC proven methodologyCustomer own methodology
Available IP: PLL, Memory, IOs and logic cellsBasic cell library
Production ready tapeoutN/A
DFT, ATPG and BIST includedN/A
Deliver fully tested packaged partsDeliver non tested dies
Schedule 8 weeks from tapeoutSchedule about 12 weeks from tapeout
High volume supportN/A



BaySand’s IP Wizard on the Web

BaySand provides Xpresso, which mimics the functionality of IP wizards commonly found in FPGA SW, to facilitate the designers ability to generate the desired IP function for the application and customization. The user interface is intuitive and similar to FPGA IP wizards for various IPs and generates all files need for implementation and verification.

Xpresso Features

  • Web-based IP Generator (login required)
    • No installation or HW required
    • Real-time updates fro added features & support
  • Generates IP to be instantiated in the user’s design
    • IP modules for simulation & synthesis (Verilog)
    • Instantiation example
    • Automated testbench for simulation to confirm options and functionality
BaySand's XPresso

XpressIP Wizards Available

Wizards AvailableIP Types Generated
MemorySP, TDP, SDP, SPROM, DPROM, Register File
Shift Register, FIFOShift Register w/ Taps, SCFIFO, DCFIFO
PLLReconfigurable PLL various mode
IOAll supported IO standards
Soft CDRSoft Clock-Data-Recovery
DDR ControllerDDR2/DDR3 Controller with PHY
InterfaceTri-Speed Ethernet, PCI Express, XAUI, Custom SERDES PHY