BaySand Inc., a supplier of ASIC/IP platforms, today announced the immediate availability of DDR3/DDR3L/LPDDR3 memory controller and PHY IPs as part of its mcFPGA/mcASIC families. BaySand’s DDR IP provides a complete interface IP solution for applications requiring high memory throughput, optimal signal reliability for different memory topologies, and maximum reprogrammability across devices using BaySand’s proprietary MCSC technology.

BaySand Announces Immediate Availability of DDR3/DDR3L/LPDDR3 Complete Solution and Licensing For mcFPGA and mcASIC

BaySand Inc., a supplier of ASIC/IP platforms, today announced the immediate availability of DDR3/DDR3L/LPDDR3 memory controller and PHY IPs as part of its mcFPGA/mcASIC families. BaySand’s DDR IP provides a complete interface IP solution for applications requiring high memory throughput, optimal signal reliability for different memory topologies, and maximum reprogrammability across devices using BaySand’s proprietary MCSC technology.

The IP solution supports up to 1600MT/s for DDR3/DDR3L/LPDDR3 and is backward compatible with DDR2 down to 400MT/s. The DDR IP is available as a soft core for the controller, while the PHY is provided as a hardened IP for a range of floorplan configurations. Both IPs can be instantiated in mcFPGA/mcASIC family devices directly, and each controller or PHY IP can be licensed individually. The PHY includes a DFI 3.1-compliant interface, combined with a full spectrum of calibration techniques to maximize timing and voltage margin. The controller includes an AXI interface for ease of integration with customer logic. With the combined offering of both the controller and PHY IP, Baysand helps to significantly lower integration risk for customers requiring first silicon success.

BaySand can also provide additional DDR related services including PHY signal/power integrity analysis and hardening for unique floorplan configurations – please contact BaySand for more details.